W83627DHG Datasheet, PDF (85/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
8.30 Configuration Register - Index 40h (Bank 0)
Register Location:
40h
Power on Default Value: 03h
Attribute:
Read/Write
Size:
8 bits
7 6 54321 0
START
SMI#Enable
Reserved
INT_Clear
Reserved
Reserved
Reserved
INITIALIZATION
Bit 7: A one restores the power-on default values to some registers. This bit clears itself since the
power-on default of this bit is zero.
Bit 6-4: Reserved
Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status Registers. The
device will stop monitoring. It will resume upon clearing of this bit.
Bit 2: Reserved
Bit 1: A one enables the SMI# Interrupt output.
Bit 0: A one enables startup of monitoring operations; a zero puts the part in standby mode.
Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an
interrupt has occurred unlike "INT_Clear'' bit.
8.31 Interrupt Status Register 1 - Index 41h (Bank 0)
Register Location:
41h
Power on Default Value: 00h
Attribute:
Read Only
Size:
8 bits
7 6 5 4321 0
CPUVCORE
VIN0
AVCC(Pin95)
3VCC
SYSTIN
CPUTIN
SYSFANIN
CPUFANIN0
Bit 7: A one indicates the fan count limit of CPUFANIN0 has been exceeded.
Bit 6: A one indicates the fan count limit of SYSFANIN has been exceeded.
Bit 5: A one indicates the high limit of CPUTIN temperature has been exceeded.
Publication Release Date: Aug, 22, 2007
-73-
Version 1.4