W83627DHG Datasheet, PDF (218/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
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BIT READ / WRITE
1 Reserved.
0
R/W
DESCRIPTION
ATXPGD signal to control PWROK and PWROK2 generation
0: Enable.
1: Disable.
* This bit is available both for UBE and UBF version
CR E6h. (Default 1Ch)
BIT READ / WRITE
DESCRIPTION
ENMDAT => (VSB)
7
R/W
Three keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY,
CRE0[1]) define the combinations of the mouse wake-up events. Please
see the table in CRE0, bit 4 for the details.
6 Reserved.
CASEOPEN Clear Control. (VSB)
5
R/W
Write 1 to this bit to clear CASEOPEN status. This bit will not clear the status
itself. Please write 0 after an event is cleared. The function is the same as
Index 46h bit 7 of H/W Monitor part.
Power-loss Last State Flag. (VBAT)
4
R/W
0: ON
1: OFF.
PWROK_DEL (first stage) (VSB)
Set the delay time when rising from PWROK_LP to PWROK_ST.
3
R/W
0: 300 ~ 500 mS.
1: 200 ~ 300 mS.
2~1
R/W
PWROK_DEL (VSB)
Set the delay time when rising from PWROK_ST to PWROK.
00: No delay time.
01: Delay 32 mS
10: 96 mS
11: Delay 250 mS
0
R / W-Clear
PWROK_TRIG =>
Write 1 to re-trigger the PWROK signal from low to high.
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Publication Release Date: Aug, 22, 2007
Version 1.4