W83627DHG Datasheet, PDF (136/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
10.2 Register Descriptions
There are several status, data, and control registers in the W83627DHG. These registers are defined
below, and the rest of this section provides more details about each one of them.
ADDRESS
OFFSET
base address + 0
base address + 1
base address + 2
base address + 3
base address + 4
base address + 5
base address + 7
REGISTER
READ
WRITE
SA REGISTER
SB REGISTER
TD REGISTER
MS REGISTER
DT (FIFO) REGISTER
DI REGISTER
DO REGISTER
TD REGISTER
DR REGISTER
DT (FIFO) REGISTER
CC REGISTER
10.2.1 Status Register A (SA Register) (Read base address + 0)
Along with the SB register, the SA register is used to monitor several disk-interface pins in PS/2 and
Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:
7 6 5 4 3 ²¹ 0
DIR
WP#
INDEX#
HEAD
TRAK0#
STEP
DRV2#
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
RESERVED (Bit 6)
STEP (Bit 5):
This bit indicates the complement of the STEP# output.
TRAK0#(Bit 4):
This bit indicates the value of the TRAK0# input.
HEAD (Bit 3):
This bit indicates the complement of the HEAD# output.
0 side 0
1 side 1
-124-
Publication Release Date: Aug, 22, 2007
Version 1.4