W83627DHG Datasheet, PDF (88/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
7 6 54321 0
Reserved
CPUFANIN1
AUXFANIN1
Reserved
Reserved
Reserved
Reserved
CaseOpen Clear
Bit 7: CASEOPEN Clear Control. Write 1 to this bit will clear CASEOPEN status. This bit won’t be self
cleared, please write 0 after event be cleared. The function is the same as LDA, CR[E6h] bit 5.
Bit 6-3: Reserved.
Bit 2-1: A one disables the corresponding interrupt status bit for the SMI interrupt. (See Interrupt
Status Register 3 - Index 50h (Bank 4))
Bit 0: Reserved.
8.37 Fan Divisor Register I - Index 47h (Bank 0)
Register Location:
47h
Power on Default Value: 55h
Attribute:
Read/Write
Size:
8 bits
7 654 32 1 0
FANINC5
FANOPV5
FANINC4
FANOPV4
SYSFANIN DIV_B0
SYSFANIN DIV_B1
CPUFANIN0 DIV_B0
CPUFANIN0 DIV_B1
Bit 7-6: CPUFANIN0 Divisor, bits1-0. (See VBAT Monitor Control Register - Index 5Dh (Bank 0))
Bit 5-4: SYSFANIN Divisor, bits1-0. (See VBAT Monitor Control Register - Index 5Dh (Bank 0))
Bit 3: CPUFANIN1 output value, only if bit 2 is set to zero. Otherwise, this bit has no meaning.
1: Pin119(CPUFANIN1) generates a logic-high signal.
0: Pin119 generates a logic-low signal. (Default)
Bit 2: CPUFANIN1 Input Control.
1: Pin119 (CPUFANIN1) acts as a FAN tachometer input. (Default)
0: Pin119 acts as a FAN control signal, and the output value is set by register bit 3.
Bit 1: AUXFANIN1 output value, only if bit 0 is set to zero. Otherwise, this bit has no meaning.
1: Pin58(AUXFANIN1) generates a logic-high signal.
0: Pin58 generates a logic-low signal. (Default)
Bit 0: AUXFANIN1 Input Control.
Publication Release Date: Aug, 22, 2007
-76-
Version 1.4