W83627DHG Datasheet, PDF (183/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
Table 14.4
SYMBOL
PARAMETER
MIN
MAX
t3
FTPRST# active to PWROK active
28
39
Note. 1. The values above are the worst-case results of R&D simulation
2. The length of T_L level is based on the length of the low level of FTPRST#
UNIT
mS
Additionally, the ATXPGD signal, too, is used to control the generation of PWROK and PWROK2. In
Figure 14.8, the 3VCC voltage rises to “V3”, and then starts a delay – “t2” for PWROK and PWROK2
generation. However, ATXPGD is still inactive after t2; therefore the delay time before the rising edge
of PWROK and PWROK2 are t2 plus Td. The length of Td is based on when the ATXPGD signal is
active. Once 3VCC falls below “V4” or the ATXPGD signal is inactive, PWROK and PWROK2 de-assert
immediately.
3VCC ^V3
PWROK/PWROK2 are
active when both 3VCC
and ATXPGD are valid
V4
ATXPGD(input)
t2
PWROK/PWROK2
(output)
Td
Figure 14.8
PWROK/PWROK2
are inactive when
either 3VCC or
ATXPGD is invalid
In Figure 14.9, the 3VCC voltage rises to “V3”, and the ATXPGD is active during t2, so PWROK and
PWROK2 assert after t2. The timing of t2 starts when 3VCC voltage rises to “V3”. No matter the
ATXPGD signal activation is during or after t2, PWROK and PWROK2 assert or de-assert according to
the 3VCC voltage and the ATXPGD signal.
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Publication Release Date: Aug, 22, 2007
Version 1.4