W83627DHG Datasheet, PDF (69/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
8.3 SYSFANOUT PWM Output Frequency Configuration Register - Index 00h
(Bank 0)
Register Location:
00h
Power on Default Value: 04h
Attribute:
Read/Write
Size:
8 bits
7 6 5 43 2 1 0
PWM_SCALE1
PWM_CLK_SEL1
The register is meaningful only when SYSFANOUT is programmed for PWM output (i.e.,
Bank0 Index 04h, bit 0 is 0).
Bit 7: SYSFANOUT PWM Input Clock Source Select. This bit selects the clock source for PWM output
frequency.
0: clock source is 24 MHz.
1: clock source is 180 KHz.
Bit 6-0: SYSFANOUT PWM Pre-Scale divider. The clock source for PWM output is divided by this
seven-bit value to calculate the actual PWM output frequency.
PWM output frequency = ^{Input Clock} ∗ ¹
Pre_Scale Divider 256
The maximum value of the divider is 127 (7Fh), and it should not be set to 0.
8.4 SYSFANOUT Output Value Select Register - Index 01h (Bank 0)
Register Location:
01h
Power on Default Value: FFh
Attribute:
Read/Write
Size:
8 bits
7 6 5 4 32 1 0
SYSFANOUT Value
Publication Release Date: Aug, 22, 2007
-57-
Version 1.4