W83627DHG Datasheet, PDF (167/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
12.3.10 ECR (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows:
76
543
21
0
empty
full
service Intr
dmaEn
nErrIntrEn
MODE
MODE
MODE
Bit 7-5: Read/Write. These bits select the mode.
000 Standard Parallel Port (SPP) mode. The FIFO is reset in this mode.
001 PS/2 Parallel Port mode. In addition to the functions of the SPP mode, this mode has
an extra trait: Direction is able to tri-state the data lines. Furthermore, reading the
data register returns the value on the data lines, not the value in the data register.
010 Parallel Port FIFO mode. This is the same as SPP mode except that bytes are
written or DMAed to the FIFO. FIFO data are automatically transmitted using the
standard parallel port protocol. This mode functions only when direction is 0.
011 ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed
into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and
automatically transmitted to the peripheral using the ECP Protocol. When the
direction is 1 (reverse direction), bytes are moved from the ECP parallel port and
packed into bytes in the ecpDFifo.
100 EPP Mode. EPP mode is activated if the EPP mode is selected.
101 Reserved.
110 Test Mode. The FIFO may be written and read in this mode, but the data is not
transmitted on the parallel port.
111 Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
Bit 4: Read/Write (Valid only in ECP Mode)
1
Disables the interrupt generated on the asserting edge of nFault.
0
Enables the interrupt generated on the falling edge of nFault. This prevents
interrupts from being lost in the time between the read of the ECR and the write of
the ECR.
Bit 3: Read/Write
1
Enables DMA.
0
Disables DMA unconditionally.
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Publication Release Date: Aug, 22, 2007
Version 1.4