W83627DHG Datasheet, PDF (163/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
12.3.1 ECP Register and Bit Map
The next two tables list the registers used in the ECP mode and provide a bit map of the parallel port
and ECP registers.
NAME
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
ADDRESS
Base+000h
Base+000h
Base+001h
Base+002h
Base+400h
Base+400h
Base+400h
Base+400h
Base+401h
Base+402h
I/O
ECP MODES
FUNCTION
R/W
000-001
Data Register
R/W
011
ECP FIFO (Address)
R
All
Status Register
R/W
All
Control Register
R/W
010
Parallel Port Data FIFO
R/W
011
ECP FIFO (DATA)
R/W
110
Test FIFO
R
111
Configuration Register A
R/W
111
Configuration Register B
R/W
All
Extended Control Register
Note: The base addresses are specified by CR60 and 61, which are determined by the configuration register or the hardware
setting.
Data
ecpAFifo
Dsr
Dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
Ecr
D7
D6
D5
PD7
PD6
PD5
Addr/RLE Address or RLE field
nBusy
nAck
PError
1
1
Directio
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
0
0
0
compress intrValue
1
MODE
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
D4
PD4
Select
ackIntEn
1
1
nErrIntrEn
D3
PD3
nFault
SelectIn
0
1
dmaEn
D2
D1
PD2
PD1
1
1
nInit
autofd
0
0
1
1
serviceIntr full
D0
PD0
1
strobe
0
1
empty
NOTE
2
1
1
2
2
2
Each register (or pair of registers, in some cases) is discussed below.
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Publication Release Date: Aug, 22, 2007
Version 1.4