W83627DHG Datasheet, PDF (21/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
5.1 LPC Interface
SYMBOL
IOCLK
PME#
PCICLK
LDRQ#
SERIRQ
LAD[3:0]
LFRAME#
LRESET#
PIN
18
86
21
22
23
24-27
29
30
I/O
IN_tp3
OD_12p3
IN_tsp3
O_12p3
I/OD_12tp3
I/O_12tp3
IN_tsp3
IN_tsp3
DESCRIPTION
System clock input, either 24MHz or 48MHz. The actual frequency
must be specified in the register. The default value is 48MHz.
Generated PME event.
PCI-clock 33-MHz input.
Encoded DMA Request signal.
Serialized IRQ input / output.
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
Indicates the start of a new cycle or the termination of a broken
cycle.
Reset signal. It can be connected to the PCIRST# signal on the
host.
5.2 FDC Interface
SYMBOL
DRVDEN0
INDEX#
MOA#
DSA#
DIR#
STEP#
WD#
WE#
TRAK0#
PIN I/O
DESCRIPTION
1 OD₂₄ Drive Density Select bit 0.
This Schmitt-trigger input from the disk drive is active-low when the
3
IN_cs
head is positioned over the beginning of a track marked by an index
hole. This input pin needs to connect a pulled-up 1-KΩ resistor to 5V for
Floppy Drive compatibility.
4
OD₂₄
Motor A On. When set to 0, this pin activates disk drive A. This is an
open-drain output.
6
OD₂₄
Drive Select A. When set to 0, this pin activates disk drive A. This is an
open-drain output.
Direction of the head step motor. An open-drain output.
8 OD₂₄ Logic 1 = outward motion
Logic 0 = inward motion
9
OD₂₄
Step output pulses. This active-low open-drain output produces a
pulse to move the head to another track.
10
OD₂₄
Write data. This logic-low open-drain writes pre-compensation serial
data to the selected FDD. An open-drain output.
11 OD₂₄ Write enable. An open-drain output.
Track 0. This Schmitt-trigger input from the disk drive is active-low
13
IN_cs
when the head is positioned over the outermost track. This input pin
needs to connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive
compatibility.
Publication Release Date: Aug, 22, 2007
-9-
Version 1.4