W83627DHG Datasheet, PDF (181/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
SYMBOL
PARAMETER
V1 3VSB Valid Voltage
MIN. TYP.
2.4 2.6
V2 3VSB Ineffective Voltage
2.25 2.4
V1 3VSB Valid Voltage
-
-
V2 3VSB Ineffective Voltage
2.4 -
t1 Valid 3VSB to RSMRST# inactive 100 -
Table 14.2
MAX.
2.75
2.55
3.1
-
200
UNIT
V
V
V
V
mS
NOTE
For both UBC and
UBE version
For both UBC and
UBE version
For UBF version
For UBF version
14.4 PWROK Generation
The PWROK (Pin 71) signal is an output and is used as the 3VCC power-on reset signal.
When the W83627DHG detects the 3VCC voltage rises to “V3”, it then starts a delay – “t2” before the
rising edge of PWROK asserting. If the 3VCC voltage falls below “V4”, the PWROK de-asserts
immediately.
Timing and voltage parameters are shown in Figure 14.6 and Table 14.3.
t2
PWROK
V3
3VCC
V4
Figure 14.6
SYMBOL
PARAMETER
V3 3VCC Valid Voltage
V4 3VCC Ineffective Voltage
V3 3VCC Valid Voltage
V4 3VCC Ineffective Voltage
t2 Valid 3VCC to PWROK active
MIN. TYP. MAX. UNIT
2.4 2.6 2.75 V
2.25 2.4 2.55 V
-
- 3.1 V
2.4 -
-
V
300 - 500 mS
Table 14.3
NOTE
For both UBC and UBE
version
For both UBC and UBE
version
For UBF version
For UBF version
Originally, the t2 timing is between 300 mS to 500 mS, but it can be changed to 200 mS to 300 mS by
programming Logical Device A, CR[E6h], bit 3 to “1”. Furthermore, the W83627DHG provides four
different extra delay time of PWROK for various demands. The four extra delay time are designed at
-169-
Publication Release Date: Aug, 22, 2007
Version 1.4