W83627DHG Datasheet, PDF (9/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
8.67 CPUFANOUT0 Critical Temperature Register - Index 6Ch (Bank 0) ................................... 93
8.68 AUXFANOUT Critical Temperature Register - Index 6Dh (Bank 0) ..................................... 93
8.69 CPUFANOUT1 Critical Temperature Register - Index 6Eh (Bank 0) ................................... 94
8.70 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1)...... 94
8.71 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1) ...... 95
8.72 CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1)........................ 95
8.73 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1) ......... 96
8.74 CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) .......... 96
8.75 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1)97
8.76 CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank
1)…….................................……………………………………………………………………………….97
8.77 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2)...... 98
8.78 AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2)....... 98
8.79 AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2) ........................ 98
8.80 AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2).......... 99
8.81 AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) .......... 99
8.82 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank
2)……............................................................................................................................................ 100
8.83 AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank
2)……............................................................................................................................................ 100
8.84 Interrupt Status Register 3 - Index 50h (Bank 4) ................................................................ 101
8.85 SMI# Mask Register 4 - Index 51h (Bank 4) ....................................................................... 102
8.86 Reserved Register - Index 52h (Bank 4)............................................................................. 102
8.87 BEEP Control Register 3 - Index 53h (Bank 4)................................................................... 102
8.88 SYSTIN Temperature Sensor Offset Register - Index 54h (Bank 4) .................................. 103
8.89 CPUTIN Temperature Sensor Offset Register - Index 55h (Bank 4).................................. 103
8.90 AUXTIN Temperature Sensor Offset Register - Index 56h (Bank 4) .................................. 104
8.91 Reserved Register - Index 57h-58h (Bank 4) ..................................................................... 104
8.92 Real Time Hardware Status Register I - Index 59h (Bank 4).............................................. 104
8.93 Real Time Hardware Status Register II - Index 5Ah (Bank 4) ............................................ 105
8.94 Real Time Hardware Status Register III - Index 5Bh (Bank 4) ........................................... 106
8.95 Reserved Register - Index 5Ch ~ 5Fh (Bank 4).................................................................. 107
8.96 Value RAM 2 ⎯ Index 50h-59h (Bank 5)............................................................................ 107
8.97 Reserved Register - Index 50h ~ 57h (Bank 6) .................................................................. 107
9. SERIAL PERIPHERAL INTERFACE............................................................................................ 108
9.1 Using the SPI Interface via the LPC ................................................................................... 108
10. FLOPPY DISK CONTROLLER..................................................................................................... 111
10.1 FDC Functional Description ................................................................................................ 111
10.1.1 FIFO (Data)..........................................................................................................................111
10.1.2 Data Separator.....................................................................................................................112
10.1.3 Write Precompensation........................................................................................................112
10.1.4 Perpendicular Recording Mode............................................................................................112
10.1.5 FDC Core.............................................................................................................................112
Publication Release Date: Aug, 22, 2007
-VII-
Version 1.4