W83627DHG Datasheet, PDF (11/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
12.3.10 ECR (Extended Control Register) Mode = all ......................................................................155
12.3.11 ECP Pin Descriptions...........................................................................................................156
12.3.12 ECP Operation.....................................................................................................................157
12.3.13 FIFO Operation ....................................................................................................................158
12.3.14 DMA Transfers.....................................................................................................................158
12.3.15 Programmed I/O (NON-DMA) Mode ....................................................................................158
13. KEYBOARD CONTROLLER ........................................................................................................ 159
13.1 Output Buffer ....................................................................................................................... 159
13.2 Input Buffer.......................................................................................................................... 159
13.3 Status Register.................................................................................................................... 160
13.4 Commands .......................................................................................................................... 160
13.5 Hardware GATEA20/Keyboard Reset Control Logic .......................................................... 162
13.5.1 KB Control Register .............................................................................................................162
13.5.2 Port 92 Control Register.......................................................................................................163
14. POWER MANAGEMENT EVENT ................................................................................................ 164
14.1 Power Control Logic............................................................................................................ 164
14.1.1 PSON# Logic .......................................................................................................................165
14.1.2 AC Power Failure Resume...................................................................................................166
14.2 Wake Up the System by Keyboard and Mouse .................................................................. 167
14.2.1 Waken up by Keyboard events ............................................................................................167
14.2.2 Waken up by Mouse events.................................................................................................167
14.3 Resume Reset Logic........................................................................................................... 168
14.4 PWROK Generation............................................................................................................ 169
14.4.1 The Relation among PWROK/PWROK2, ATXPGD and FTPRST# - both for UBE and UBF
Version Only.......................................................................................................................................170
15. SERIALIZED IRQ.......................................................................................................................... 173
15.1 Start Frame ......................................................................................................................... 173
15.2 IRQ/Data Frame.................................................................................................................. 174
15.3 Stop Frame.......................................................................................................................... 175
16. WATCHDOG TIMER .................................................................................................................... 176
17. GENERAL PURPOSE I/O ............................................................................................................ 177
18. VID INPUTS AND OUTPUTS ....................................................................................................... 178
18.1 VID Input Detection ............................................................................................................. 178
18.2 VID Output Control.............................................................................................................. 178
19. PCI RESET BUFFERS ................................................................................................................. 179
20. CONFIGURATION REGISTER .................................................................................................... 180
20.1 Chip (Global) Control Register ............................................................................................ 180
20.2 Logical Device 0 (FDC) ....................................................................................................... 187
20.3 Logical Device 1 (Parallel Port)........................................................................................... 190
20.4 Logical Device 2 (UART A) ................................................................................................. 191
20.5 Logical Device 3 (UART B) ................................................................................................. 191
20.6 Logical Device 5 (Keyboard Controller) .............................................................................. 193
Publication Release Date: Aug, 22, 2007
-IX-
Version 1.4