W83627DHG Datasheet, PDF (151/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
11.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of data transfer during communication.
7654 321 0
RBR Data ready (RDR)
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to logical 0. In 16550 mode, this bit is set to logical 1
when there is at least one parity-bit error and no stop-bit error or silent-byte detected in the FIFO.
In 16550 mode, this bit is cleared to logical 0 by reading from the USR if there are no remaining
errors left in the FIFO.
Bit 6: TSRE. In 16450 mode, this bit is set to logical 1 when TBR and TSR are both empty. In 16550
mode, it is set to logical 1 when the transmit FIFO and TSR are both empty. Otherwise, this bit is
set to logical 0.
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit is set to
logical 1. If ETREI of ICR is high, an interrupt is generated to notify the CPU to write the next
data. In 16550 mode, this bit is set to logical 1 when the transmit FIFO is empty. It is set to logical
0 when the CPU writes data into TBR or the FIFO.
Bit 4: SBD. This bit is set to logical 1 to indicate that received data are kept in silent state for the time it
takes to receive a full word, which includes the start bit, data bits, parity bit, and stop bits. In
16550 mode, it indicates the same condition for the data on the top of the FIFO. When the CPU
reads USR, it sets this bit to logical 0.
Bit 3: NSER. This bit is set to logical 1 to indicate that the received data have no stop bit. In 16550
mode, it indicates the same condition for the data on the top of the FIFO. When the CPU reads
USR, it sets this bit to logical 0.
Bit 2: PBER. This bit is set to logical 1 to indicate that the received data has the wrong parity bit. In
16550 mode, it indicates the same condition for the data on the top of the FIFO. When the CPU
reads USR, it sets this bit to logical 0.
Bit 1: OER. This bit is set to logical 1 to indicate that the received data have been overwritten by the
next received data before they were read by the CPU. In 16550 mode, it indicates the same
condition, instead of FIFO full. When the CPU reads USR, it sets this bit to logical 0.
Bit 0: RDR. This bit is set to logical 1 to indicate that the received data are ready to be read by the CPU
in the RBR or FIFO. When no data are left in the RBR or FIFO, the bit is set to logical 0.
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Publication Release Date: Aug, 22, 2007
Version 1.4