W83627DHG Datasheet, PDF (4/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
PAGES DATES
8 N.A. 09/29/2006
9 N.A. 10/05/2006
10 N.A. 12/12/2006
VERSION
0.6
1.0
1.1
WEB
VERSION
MAIN CONTENTS
clock selection.
5. Modify the default values of HM Device Bank 0,
CR[43h] bit 5,0 and CR[46h] bit 2~1.
1. Add new chapters for Serial Peripheral Interface,
Configuration Register Access Protocol, Power
Management, Serialized IRQ, Watchdog Timer VID
Inputs and Outputs, and PCI Reset Buffers.
2. Update the feature lists of the W83627DHG in Chapter
2 Features.
3. Add descriptions of PECI and SST and a table of
SMBus in Chapter 5 Pin Description.
4. Add new sections of Caseopen and Beep Alarm
Function in Chapter 7 Hardware Monitor.
5. Add Clock Input Timing, PECI & SST Timing, and SPI
Timing in Chapter 21 Specifications.
6. Remove sections 9.4 and 9.5 (EXTFDD and
EXT2FDD).
7. Modify the descriptions of Hardware Monitor Device,
Bank 0, Index 59h, bits(6..4).
8. Add a beep control bit for VIN4 at Hardware Monitor
Device, Bank 0, Index 57h, bit6.
9. Remove status bit of PME# status of MIDI IRQ event at
N.A.
Logical Device A, CRF4, bit 1.
10. Remove control bit of enable/disable PME# of MIDI at
Logical Device A, CRF7, bit 1.
11. Modify the descriptions of Tape Drive Register in
Chapter 10 Floppy Disk Controller.
12. Correct the description of Digital Input Register, bit
(6-4) in Chapter 10 Floppy Disk Controller.
13. Remove the description of “MR pin” in Digital Output
Register in Chapter 10 Floppy Disk Controller.
14. Adapt “Serial Flash Interface” to “Serial Peripheral
Interface”.
15. Modify “Absolute Maximum Ratings” in Chapter 21
Specifications.
16. Remove “V_DD is 5V± 10% tolerance” from the
description of DC Characteristics in Chapter 21
Specifications.
17. Update “S5_{c o l d} state” to “S5 state.
18. Remove the section of “AT Interface” in Chapter
10 Floppy Disk Controller.
N.A. 1. Update AC Timing parameters and waveforms.
1. Update Table 9.1 and Table 9.2 in Chapter 9 Serial
Peripheral Interface
N.A. _{2. Update CR2Ah in Chapter 20 Configuration Register}
3. Modify CR24h bit 0 to reserved
Publication Release Date: Aug, 22, 2007
-II-
Version 1.4