W83627DHG Datasheet, PDF (150/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
Bit Number
Register Address
Base
0
1
2
3
4
5
6
7
Receiver
+0
Buffer
BDLAB = 0 Register
(Read Only)
RBR
RX Data RX Data
Bit 0
Bit 1
RX Data
Bit 2
RX Data
Bit 3
RX Data RX Data RX Data RX Data
Bit 4
Bit 5
Bit 6
Bit 7
Transmitter
+0
Buffer
BDLAB = 0 Register
(Write Only)
TBR
TX Data
Bit 0
TX Data
Bit 1
TX Data
Bit 2
TX Data
Bit 3
TX Data TX Data TX Data
Bit 4
Bit 5
Bit 6
TX Data
Bit 7
RBR Data TBR
USR
HSR
+1
BDLAB = 0
Interrupt
Control
Register
ICR
Ready Empty
Interrupt Interrupt
Interrupt Interrupt
Enable Enable
Enable
(ERDRI)
Enable
(ETBREI)
(EUSRI)
(EHSRI)
0
0
0
0
+2
Interrupt
Status
Register
ISR
(Read Only)
"0" if
Interrupt
Pending
Interrupt
Status
Bit (0)
Interrupt
Status
Bit (1)
Interrupt
Status
Bit (2)**
0
FIFOs FIFOs
0
Enabled Enabled
**
**
+2
UART FIFO
Control
Register
(Write Only)
UFR
FIFO
Enable
RCVR
FIFO
Reset
XMIT
FIFO
Reset
DMA
Mode
Select
Reserved Reversed
RX
Interrupt
Active
Level
(LSB)
RX
Interrupt
Active
Level
(MSB)
Data
Data
Multiple Parity
Even
Parity
Set
Baudrate
+3
UART
Control
Register
UCR
Length
Select
Bit 0
(DLS0)
Length
Select
Bit 1
(DLS1)
Stop Bits
Enable
(MSBE)
Bit
Enable
(PBE)
Parity
Enable
(EPE)
Bit Fixed
Enable
PBFE)
Silence
Enable
(SSE)
Divisor
Latch
Access Bit
(BDLAB)
+4
Handshake
Control HCR
Register
Data
Terminal
Ready
(DTR)
Request
to
Send
(RTS)
Loopback
RI
Input
IRQ
Enable
Internal
Loopback
Enable
0
0
0
+5
UART Status
Register
USR
RBR Data
Ready
Overrun
Error
(RDR) (OER)
Parity Bit
Error
(PBER)
No Stop
Bit
Error
(NSER)
Silent
Byte
Detected
(SBD)
TBR
Empty
(TBRE)
TSR
Empty
(TSRE)
RX FIFO
Error
Indication
(RFEI) **
+6
Handshake
Status
Register
HSR
CTS
Toggling
(TCTS)
DSR RI Falling
Toggling Edge
(TDSR) (FERI)
DCD
Toggling
(TDCD)
Clear
to Send
(CTS)
Data Set
Ready
(DSR)
Ring
Indicator
(RI)
Data
Carrier
Detect
(DCD)
+7
User Defined
Register
UDR
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
+0
BDLAB =
1
Baudrate
Divisor Latch
Low
BLL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
+1
Baudrate
BDLAB =
1
Divisor Latch
High
BHL
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
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Publication Release Date: Aug, 22, 2007
Version 1.4