W83627DHG Datasheet, PDF (171/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
13. KEYBOARD CONTROLLER
The W83627DHG KBC (8042 with licensed KB BIOS) circuit is designed to provide the functions
needed to interface a CPU with a keyboard and/or a PS/2 mouse and can be used with
IBM^®-compatible personal computers or PS/2-based systems. The controller receives serial data from
the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a
byte of data in its output buffer. Then, the controller asserts an interrupt to the system when data are
placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data
transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an
acknowledgement is received for the previous data byte.
KINH
GP I/O PINS
Multiplex I/O PINS
P24
P25
P21
P17
P20
P27
8042
P10
P26
T0
P12~P16
P23
T1
P22
P11
Keyboard and Mouse Interface
KIRQ
MIRQ
GATEA20
KBRST
KDAT
KCLK
MCLK
MDAT
13.1 Output Buffer
The output buffer is an 8-bit, read-only register at I/O address 60h (Default, PnP programmable I/O
address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan
code (from the keyboard) and required command bytes to the system. The output buffer can only be
read when the output buffer full bit in the register (in the status register) is logical 1.
13.2 Input Buffer
The input buffer is an 8-bit, write-only register at I/O address 60h or 64h (Default, PnP programmable
I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60h sets a flag to
indicate a data write; writing to address 64h sets a flag to indicate a command write. Data written to I/O
address 60h is sent to the keyboard (unless the keyboard controller is expecting a data byte) through
the controller's input buffer only if the input buffer full bit (in the status register) is logical 0.
-159-
Publication Release Date: Aug, 22, 2007
Version 1.4