W83627DHG Datasheet, PDF (10/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
10.1.6 FDC Commands ..................................................................................................................113
10.2 Register Descriptions .......................................................................................................... 124
10.2.1 Status Register A (SA Register) (Read base address + 0) ..................................................124
10.2.2 Status Register B (SB Register) (Read base address + 1) ..................................................126
10.2.3 Digital Output Register (DO Register) (Write base address + 2)..........................................128
10.2.4 Tape Drive Register (TD Register) (Read base address + 3) ..............................................128
10.2.5 Main Status Register (MS Register) (Read base address + 4) ............................................129
10.2.6 Data Rate Register (DR Register) (Write base address + 4) ...............................................129
10.2.7 FIFO Register (R/W base address + 5)................................................................................131
10.2.8 Digital Input Register (DI Register) (Read base address + 7) ..............................................133
10.2.9 Configuration Control Register (CC Register) (Write base address + 7)..............................134
11. UART PORT ................................................................................................................................. 136
11.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)................................... 136
11.2 Register Description............................................................................................................ 136
11.2.1 UART Control Register (UCR) (Read/Write) ........................................................................136
11.2.2 UART Status Register (USR) (Read/Write)..........................................................................139
11.2.3 Handshake Control Register (HCR) (Read/Write)................................................................140
11.2.4 Handshake Status Register (HSR) (Read/Write) .................................................................140
11.2.5 UART FIFO Control Register (UFR) (Write only) .................................................................141
11.2.6 Interrupt Status Register (ISR) (Read only) .........................................................................142
11.2.7 Interrupt Control Register (ICR) (Read/Write) ......................................................................143
11.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) ....................................................143
11.2.9 User-defined Register (UDR) (Read/Write)..........................................................................144
12. PARALLEL PORT......................................................................................................................... 145
12.1 Printer Interface Logic ......................................................................................................... 145
12.2 Enhanced Parallel Port (EPP)............................................................................................. 146
12.2.1 Data Port (Data Swapper)....................................................................................................147
12.2.2 Printer Status Buffer.............................................................................................................147
12.2.3 Printer Control Latch and Printer Control Swapper ..............................................................147
12.2.4 EPP Address Port ................................................................................................................148
12.2.5 EPP Data Port 0-3 ...............................................................................................................148
12.2.6 EPP Pin Descriptions ...........................................................................................................149
12.2.7 EPP Operation .....................................................................................................................149
12.3 Extended Capabilities Parallel (ECP) Port.......................................................................... 150
12.3.1 ECP Register and Bit Map ...................................................................................................151
12.3.2 Data and ecpAFifo Port........................................................................................................152
12.3.3 Device Status Register (DSR)..............................................................................................152
12.3.4 Device Control Register (DCR) ............................................................................................153
12.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010......................................................................153
12.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011 ..........................................................................153
12.3.7 TFIFO (Test FIFO Mode) Mode = 110 .................................................................................154
12.3.8 CNFGA (Configuration Register A) Mode = 111 ..................................................................154
12.3.9 CNFGB (Configuration Register B) Mode = 111 ..................................................................154
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Publication Release Date: Aug, 22, 2007
Version 1.4