W83627DHG Datasheet, PDF (29/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
5.8 PECI Interface
SYMBOL
PIN
PECI
108
Vtt
107
PECISB
106
I/O
I/O_V3
Power
I/OB_V3
DESCRIPTION
INTEL^® CPU PECI interface. Connect to CPU.
INTEL^® CPU Vtt Power. This pin is connected to GND if the PECI
function is not in use.
INTEL^® CPU PECI interface. Connect to ICH8.
5.9 SST Interface
SYMBOL
PIN
SST
114
I/O
I/O_V4
DESCRIPTION
Simple Serial Transport (SST) Interface.
5.10 Advanced Configuration and Power Interface
The Advanced Configuration and Power Interface (ACPI) is an interface that allows OS-directed Power
Management (OSPM). The ACPI replaces the APM (Advanced Power Management), MPS
(Multiprocessor Specification), and PnP BIOS Specification. In addition to power management, the
ACPI supports the functions of thermal management, state management, and speed control, as well as
the global system states and different device power states. Two of the primary states that the
W83627DHG supports are the S0 (working) and S3 (suspend to RAM) states. S0 is a full-power state,
in which the computer is actively used. S3 is a sleeping state, in which the processor is powered down,
but the memory, where the last procedural state is stored, is still active. By employing the ACPI, the
system conserves more energy through transiting unused devices into lower power states, including
placing the entire system in a low-power state when possible.
SYMBOL
PIN
PSIN#
68
GP56
PSOUT#
67
GP57
RSMRST#
75
GP51
SUSB#
73
GP52
PSON#
72
GP53
PWROK
71
GP54
I/O
IN_tu
I/OD_12t
OD₁₂
I/OD_12t
OD12
I/OD12t
INt
I/OD12t
OD12
I/OD12t
OD12
I/OD12t
DESCRIPTION
Panel Switch Input. This pin is active-low with an internal
pulled-up resistor.
General-purpose I/O port 5 bit 6.
Panel Switch Output. This signal is used to wake-up the system
from S3/S5 state.
General-purpose I/O port 5 bit 7.
Resume reset signal output.
General-purpose I/O port 5 bit 1.
System S3 state input.
General-purpose I/O port 5 bit 2.
Power supply on-off output.
General-purpose I/O port 5 bit 3.
This pin generates the PWROK signal while 3VCC comes in.
General-purpose I/O port 5 bit 4.
Publication Release Date: Aug, 22, 2007
-17-
Version 1.4