W83627DHG Datasheet, PDF (165/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
Bit 7: This bit reflects the complement of the Busy input.
Bit 6: This bit reflects the nAck input.
Bit 5: This bit reflects the PError input.
Bit 4: This bit reflects the Select input.
Bit 3: This bit reflects the nFault input.
Bit 2-0: These three bits are not implemented and are always logical 1 during a read.
12.3.4 Device Control Register (DCR)
The bit definitions are as follows:
7 65 432 1 0
11
strobe
autofd
nInit
SelectIn
ackIntEn
Direction
Bit 7, 6: These two bits are always read as logical one and cannot be written.
Bit 5: If the mode is 000 or 010, this bit has no effect and the direction is always out. In other modes,
0 the parallel port is in output mode.
1 the parallel port is in input mode.
Bit 4: Interrupt request enable. When this bit is set to logical 1, it enables interrupt requests from the
parallel port to the CPU on the low-to-high transition on ACK#.
Bit 3: This bit is inverted and output to the SLIN# output.
0 The printer is not selected.
1 The printer is selected.
Bit 2: This bit is output to the INIT# output.
Bit 1: This bit is inverted and output to the AFD# output.
Bit 0: This bit is inverted and output to the STB# output.
12.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010
This mode is defined only for the forward direction. Bytes written or DMAed to this FIFO are transmitted
by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the
FIFO are byte-aligned.
12.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011
When the direction bit is 0, bytes written or DMAed to this FIFO are transmitted by a hardware
handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are
byte-aligned.
When the direction bit is 1, data bytes from the peripheral are read via automatic hardware handshake
from ECP into this FIFO. Reads or DMAs from the FIFO return bytes of ECP data to the system.
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Publication Release Date: Aug, 22, 2007
Version 1.4