W83627DHG Datasheet, PDF (160/268 Pages) Winbond – WINBOND LPC I/O

W83627DHG
When this bit is logical 1, the parallel port is in input mode (read); when it is logical 0, the parallel port is
in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and fixed at
zero.
Bit 4: A logical 1 allows an interrupt to occur when ACK# changes from low to high.
Bit 3: A logical 1 selects the printer.
Bit 2: A logical 0 starts the printer (50 microsecond pulse, minimum).
Bit 1: A logical 1 causes the printer to line-feed after a line is printed.
Bit 0: A logical 1 generates an active-high pulse for a minimum of 0.5μs to clock data into the printer.
Valid data must be present for a minimum of 0.5μs before and after the strobe pulse.
12.2.4 EPP Address Port
The address port is available only in EPP mode. Bit definitions are as follows:
7 6 5 43 2 1 0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
operation. The leading edge of IOW# causes an EPP address write cycle to be performed, and the
trailing edge of IOW# latches the data for the duration of the EPP write cycle.
PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address
read cycle to be performed and the data to be output to the host CPU.
12.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. The bit definitions for each data port are the
same and as follows:
76 5 4 3 2 1 0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
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Publication Release Date: Aug, 22, 2007
Version 1.4