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W83627DHG Datasheet, PDF (65/268 Pages) Winbond – WINBOND LPC I/O
W83627DHG
(2) Two-Times Interrupt Mode
This mode is enabled by setting Bank0 Index 4Ch, bit 6, to zero.
In this mode, the SMI# pin can create an interrupt when the current temperature rises above TO or
when the current temperature falls below THYST. Once the temperature rises above TO, however,
and generates an interrupt, this mode does not generate additional interrupts, even if the
temperature remains above TO, until the temperature falls below THYST. This interrupt must be
reset by reading all the interrupt status registers, or subsequent events do not generate interrupts.
This is illustrated in the figure above.
7.7.2 OVT# Interrupt Mode
The SMI#/OVT# pin is a multi-function pin. It can be in SMI# mode or in OVT# mode by setting
Configuration Register CR[29h], bit 6 to one or zero, respectively. In OVT# mode, it can monitor
temperatures, and it is enabled or disabled for SYSTIN, CPUTIN, and AUXTIN by Bank0 Index 18h, bit
6; Bank0 Index 4Ch, bit 3; and Bank0 Index 4Ch, bit4.
The OVT# pin has two interrupt modes, comparator and interrupt. The modes are illustrated in this
figure.
To
THYST
OVT#
(Comparator Mode; default)
OVT#
(Interrupt Mode)
*
*
*
*Interrupt Reset when Temperature sensor registers are read
If Bank0 Index 18h, bit 4, Bank1 Index 52h, bit 1, and Bank2 Index 52h, bit1 are set to zero, the OVT#
pin is in comparator mode. In comparator mode, the OVT# pin can create an interrupt once the current
temperature exceeds TO and continues to create interrupts until the temperature falls below THYST. The
OVT# pin is asserted once the temperature has exceeded TO and has not yet fallen below THYST.
If Bank0 Index 18h, bit 4, Bank1 Index 52h, bit1, and Bank2 Index 52h, bit 1 are set to one, the OVT#
pin is in interrupt mode. In interrupt mode, the OVT# pin can create an interrupt once the current
temperature rises above TO or when the temperature falls below THYST. Once the temperature rises
above TO, however, and generates an interrupt, this mode does not generate additional interrupts, even
if the temperature remains above TO, until the temperature falls below THYST. This interrupt must be
reset by reading all the interrupt status registers. The OVT# pin is asserted when an interrupt is
generated and remains asserted until the interrupt is reset.
Publication Release Date: Aug, 22, 2007
-53-
Version 1.4