C8051F120 Datasheet, PDF (9/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
List of Figures
1. System Overview.................................................................................................... 19
Figure 1.1. C8051F120/124 Block Diagram ............................................................. 21
Figure 1.2. C8051F121/125 Block Diagram ............................................................. 22
Figure 1.3. C8051F122/126 Block Diagram ............................................................. 23
Figure 1.4. C8051F123/127 Block Diagram ............................................................. 24
Figure 1.5. C8051F130/132 Block Diagram ............................................................. 25
Figure 1.6. C8051F131/133 Block Diagram ............................................................. 26
Figure 1.7. On-Board Clock and Reset .................................................................... 28
Figure 1.8. On-Chip Memory Map............................................................................ 29
Figure 1.9. Development/In-System Debug Diagram............................................... 30
Figure 1.10. MAC0 Block Diagram ........................................................................... 31
Figure 1.11. Digital Crossbar Diagram ..................................................................... 32
Figure 1.12. PCA Block Diagram.............................................................................. 33
Figure 1.13. 12-Bit ADC Block Diagram ................................................................... 35
Figure 1.14. 8-Bit ADC Diagram............................................................................... 36
Figure 1.15. DAC System Block Diagram ................................................................ 37
Figure 1.16. Comparator Block Diagram .................................................................. 38
2. Absolute Maximum Ratings .................................................................................. 39
3. Global DC Electrical Characteristics .................................................................... 40
4. Pinout and Package Definitions............................................................................ 42
Figure 4.1. C8051F120/2/4/6 Pinout Diagram (TQFP-100) ..................................... 50
Figure 4.2. C8051F130/2 Pinout Diagram (TQFP-100) ........................................... 51
Figure 4.3. TQFP-100 Package Drawing ................................................................. 52
Figure 4.4. C8051F121/3/5/7 Pinout Diagram (TQFP-64) ....................................... 53
Figure 4.5. C8051F131/3 Pinout Diagram (TQFP-64) ............................................. 54
Figure 4.6. TQFP-64 Package Drawing ................................................................... 55
5. ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)........................................................... 57
Figure 5.1. 12-Bit ADC0 Functional Block Diagram ................................................. 57
Figure 5.2. Typical Temperature Sensor Transfer Function..................................... 58
Figure 5.3. ADC0 Track and Conversion Example Timing....................................... 60
Figure 5.4. ADC0 Equivalent Input Circuits.............................................................. 61
Figure 5.5. AMX0CF: AMUX0 Configuration Register ............................................. 62
Figure 5.6. AMX0SL: AMUX0 Channel Select Register........................................... 63
Figure 5.7. ADC0CF: ADC0 Configuration Register ................................................ 64
Figure 5.8. ADC0CN: ADC0 Control Register.......................................................... 65
Figure 5.9. ADC0H: ADC0 Data Word MSB Register .............................................. 66
Figure 5.10. ADC0L: ADC0 Data Word LSB Register.............................................. 66
Figure 5.11. ADC0 Data Word Example................................................................... 67
Figure 5.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register .................. 68
Figure 5.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register.................... 68
Figure 5.14. ADC0LTH: ADC0 Less-Than Data High Byte Register........................ 69
Figure 5.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register ......................... 69
Rev. 1.3
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