C8051F120 Datasheet, PDF (248/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
R/W
SYSCKE
Bit7
R/W
T2EXE
Bit6
R/W
T2E
Bit5
R/W
INT1E
Bit4
R/W
T1E
Bit3
R/W
INT0E
Bit2
R/W
T0E
Bit1
R/W Reset Value
CP1E 00000000
Bit0
SFR Address: 0xE2
SFR Page: F
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SYSCKE: /SYSCLK Output Enable Bit.
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK (divided by 1, 2, 4, or 8) routed to Port pin. divide factor is determined by the
CLKDIV1-0 bits in register CLKSEL (See Section “14. Oscillators” on page 189).
T2EXE: T2EX Input Enable Bit.
0: T2EX unavailable at Port pin.
1: T2EX routed to Port pin.
T2E: T2 Input Enable Bit.
0: T2 unavailable at Port pin.
1: T2 routed to Port pin.
INT1E: /INT1 Input Enable Bit.
0: /INT1 unavailable at Port pin.
1: /INT1 routed to Port pin.
T1E: T1 Input Enable Bit.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
INT0E: /INT0 Input Enable Bit.
0: /INT0 unavailable at Port pin.
1: /INT0 routed to Port pin.
T0E: T0 Input Enable Bit.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
CP1E: CP1 Output Enable Bit.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
Figure 18.8. XBR1: Port I/O Crossbar Register 1
250
Rev. 1.3