C8051F120 Datasheet, PDF (195/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
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R
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Reset Value
-
-
-
PLLLCK
0
PLLSRC PLLEN PLLPWR 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x89
SFR Page: F
Bits 7-5: UNUSED: Read = 000b; Write = don’t care.
Bit 4: PLLCK: PLL Lock Flag.
0: PLL Frequency is not locked.
1: PLL Frequency is locked.
Bit 3: RESERVED. Must write to ‘0’.
Bit 2: PLLSRC: PLL Reference Clock Source Select Bit.
0: PLL Reference Clock Source is Internal Oscillator.
1: PLL Reference Clock Source is External Oscillator.
Bit 1: PLLEN: PLL Enable Bit.
0: PLL is held in reset.
1: PLL is enabled. PLLPWR must be ‘1’.
Bit 0: PLLPWR: PLL Power Enable.
0: PLL bias generator is de-activated. No static power is consumed.
1: PLL bias generator is active. Must be set for PLL to operate.
Figure 14.7. PLL0CN: PLL Control Register
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Reset Value
-
-
-
PLLM4 PLLM3 PLLM2 PLLM1 PLLM0 00000001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x8D
SFR Page: F
Bits 7-5: UNUSED: Read = 000b; Write = don’t care.
Bits 4-0: PLLM4-0: PLL Reference Clock Pre-divider.
These bits select the pre-divide value of the PLL reference clock. When set to any non-zero
value, the reference clock will be divided by the value in PLLM4-0. When set to ‘00000b’, the
reference clock will be divided by 32.
Figure 14.8. PLL0DIV: PLL Pre-divider Register
Rev. 1.3
197