C8051F120 Datasheet, PDF (194/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
14.7.3. Powering on and Initializing the PLL
To set up and use the PLL as the system clock after power-up of the device, the following procedure
should be implemented:
Step 1. Ensure that the reference clock to be used (internal or external) is running and stable.
Step 2. Set the PLLSRC bit (PLL0CN.2) to select the desired clock source for the PLL.
Step 3. Program the FLASH read timing bits, FLRT (FLSCL.5-4) to the appropriate value for the
new clock rate (see Section “15. FLASH Memory” on page 201).
Step 4. Enable power to the PLL by setting PLLPWR (PLL0CN.0) to ‘1’.
Step 5. Program the PLL0DIV register to produce the divided reference frequency to the PLL.
Step 6. Program the PLLLP3-0 bits (PLL0FLT.3-0) to the appropriate range for the divided
reference frequency.
Step 7. Program the PLLICO1-0 bits (PLL0FLT.5-4) to the appropriate range for the PLL output
frequency.
Step 8. Program the PLL0MUL register to the desired clock multiplication factor.
Step 9. Wait at least 5 µs, to provide a fast frequency lock.
Step 10. Enable the PLL by setting PLLEN (PLL0CN.1) to ‘1’.
Step 11. Poll PLLLCK (PLL0CN.4) until it changes from ‘0’ to ‘1’.
Step 12. Switch the System Clock source to the PLL using the CLKSEL register.
If the PLL characteristics need to be changed when the PLL is already running, the following procedure
should be implemented:
Step 1. The system clock should first be switched to either the internal oscillator or an external
clock source that is running and stable, using the CLKSEL register.
Step 2. Ensure that the reference clock to be used for the new PLL setting (internal or external) is
running and stable.
Step 3. Set the PLLSRC bit (PLL0CN.2) to select the new clock source for the PLL.
Step 4. If moving to a faster frequency, program the FLASH read timing bits, FLRT (FLSCL.5-4) to
the appropriate value for the new clock rate (see Section “15. FLASH Memory” on page 201).
Step 5. Disable the PLL by setting PLLEN (PLL0CN.1) to ‘0’.
Step 6. Program the PLL0DIV register to produce the divided reference frequency to the PLL.
Step 7. Program the PLLLP3-0 bits (PLL0FLT.3-0) to the appropriate range for the divided
reference frequency.
Step 8. Program the PLLICO1-0 bits (PLL0FLT.5-4) to the appropriate range for the PLL output
frequency.
Step 9. Program the PLL0MUL register to the desired clock multiplication factor.
Step 10. Enable the PLL by setting PLLEN (PLL0CN.1) to ‘1’.
Step 11. Poll PLLLCK (PLL0CN.4) until it changes from ‘0’ to ‘1’.
Step 12. Switch the System Clock source to the PLL using the CLKSEL register.
Step 13. If moving to a slower frequency, program the FLASH read timing bits, FLRT (FLSCL.5-4)
to the appropriate value for the new clock rate (see Section “15. FLASH Memory” on
page 201). Important Note: Cache reads, cache writes, and the prefetch engine should be
disabled whenever the FLRT bits are changed to a lower setting.
To shut down the PLL, the system clock should be switched to the internal oscillator or a stable external
clock source, using the CLKSEL register. Next, disable the PLL by setting PLLEN (PLL0CN.1) to ‘0’.
Finally, the PLL can be powered off, by setting PLLPWR (PLL0CN.0) to ‘0’. Note that the PLLEN and PLL-
PWR bits can be cleared at the same time.
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