C8051F120 Datasheet, PDF (220/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
3. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to
logic ‘1’).
4. Select Multiplexed mode or Non-multiplexed mode.
5. Select the memory mode (on-chip only, split mode without bank select, split mode with bank
select, or off-chip only).
6. Set up timing to interface with off-chip memory or peripherals.
Each of these five steps is explained in detail in the following sections. The Port selection, Multiplexed
mode selection, and Mode bits are located in the EMI0CF register shown in Figure 17.2.
17.3. Port Selection and Configuration
The External Memory Interface can appear on Ports 3, 2, 1, and 0 (All Devices) or on Ports 7, 6, 5, and 4
(100-pin TQFP devices only), depending on the state of the PRTSEL bit (EMI0CF.5). If the lower Ports are
selected, the EMIFLE bit (XBR2.1) must be set to a ‘1’ so that the Crossbar will skip over P0.7 (/WR), P0.6
(/RD), and if multiplexed mode is selected P0.5 (ALE). For more information about the configuring the
Crossbar, see Section “18.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 241.
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches or to the Crossbar (on Ports 3, 2, 1, and 0). See Section “18. Port Input/Out-
put” on page 239 for more information about the Crossbar and Port operation and configuration. The Port
latches should be explicitly configured to ‘park’ the External Memory Interface pins in a dormant
state, most commonly by setting them to a logic 1.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the driv-
ers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output
mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the
External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases,
the output modes of all EMIF pins should be configured for push-pull mode. See“Configuring the Output
Modes of the Port Pins” on page 242.
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