C8051F120 Datasheet, PDF (208/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
-
-
FLRT
Reserved Reserved Reserved FLWE 10000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR
Address:
SFR Address: 0xB7
SFR Page: 0
Bits 7-6: Unused.
Bits 5-4: FLRT: FLASH Read Time.
These bits should be programmed to the smallest allowed value, according to the system
clock speed.
00: SYSCLK <= 25 MHz.
01: SYSCLK <= 50 MHz.
10: SYSCLK <= 75 MHz.
11: SYSCLK <= 100 MHz.
Bits 3-1: RESERVED. Read = 000b. Must Write 000b.
Bit 0: FLWE: FLASH Write/Erase Enable.
This bit must be set to allow FLASH writes/erasures from user software.
0: FLASH writes/erases disabled.
1: FLASH writes/erases enabled.
Important Note: When changing the FLRT bits to a lower setting (e.g. when changing from a
value of 11b to 00b), cache reads, cache writes, and the prefetch engine should be
disabled using the CCH0CN register (see Figure “16.4 CCH0CN: Cache Control Regis-
ter” on page 217).
Figure 15.5. FLSCL: FLASH Memory Control
210
Rev. 1.3