C8051F120 Datasheet, PDF (13/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
15. FLASH Memory..................................................................................................... 201
Figure 15.1. FLASH Memory Map for MOVC Read and MOVX Write Operations. 203
Figure 15.2. 128k Byte FLASH Memory Map and Security Bytes.......................... 206
Figure 15.3. 64k Byte FLASH Memory Map and Security Bytes............................ 207
Figure 15.4. FLACL: FLASH Access Limit ............................................................. 208
Figure 15.5. FLSCL: FLASH Memory Control ........................................................ 210
Figure 15.6. PSCTL: Program Store Read/Write Control....................................... 211
16. Branch Target Cache ........................................................................................... 213
Figure 16.1. Branch Target Cache Data Flow ........................................................ 213
Figure 16.2. Branch Target Cache Organiztion...................................................... 214
Figure 16.3. Cache Lock Operation........................................................................ 216
Figure 16.4. CCH0CN: Cache Control Register ..................................................... 217
Figure 16.5. CCH0TN: Cache Tuning Register ...................................................... 218
Figure 16.6. CCH0LC: Cache Lock Control Register ............................................. 218
Figure 16.7. CCH0MA: Cache Miss Accumulator .................................................. 219
Figure 16.8. FLSTAT: FLASH Status ..................................................................... 219
17. External Data Memory Interface and On-Chip XRAM........................................ 221
Figure 17.1. EMI0CN: External Memory Interface Control ..................................... 223
Figure 17.2. EMI0CF: External Memory Configuration........................................... 224
Figure 17.3. Multiplexed Configuration Example.................................................... 225
Figure 17.4. Non-multiplexed Configuration Example ............................................ 226
Figure 17.5. EMIF Operating Modes ...................................................................... 227
Figure 17.6. EMI0TC: External Memory Timing Control......................................... 229
Figure 17.7. Non-multiplexed 16-bit MOVX Timing ................................................ 230
Figure 17.8. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 231
Figure 17.9. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 232
Figure 17.10. Multiplexed 16-bit MOVX Timing...................................................... 233
Figure 17.11. Multiplexed 8-bit MOVX without Bank Select Timing ....................... 234
Figure 17.12. Multiplexed 8-bit MOVX with Bank Select Timing ............................ 235
18. Port Input/Output.................................................................................................. 239
Figure 18.1. Port I/O Cell Block Diagram ............................................................... 239
Figure 18.2. Port I/O Functional Block Diagram ..................................................... 240
Figure 18.3. Priority Crossbar Decode Table ......................................................... 241
Figure 18.4. Priority Crossbar Decode Table ......................................................... 244
Figure 18.5. Priority Crossbar Decode Table ......................................................... 245
Figure 18.6. Crossbar Example:............................................................................. 247
Figure 18.7. XBR0: Port I/O Crossbar Register 0................................................... 248
Figure 18.8. XBR1: Port I/O Crossbar Register 1................................................... 249
Figure 18.9. XBR2: Port I/O Crossbar Register 2................................................... 250
Figure 18.10. P0: Port0 Data Register ................................................................... 251
Figure 18.11. P0MDOUT: Port0 Output Mode Register ......................................... 251
Figure 18.12. P1: Port1 Data Register ................................................................... 252
Figure 18.13. P1MDIN: Port1 Input Mode Register................................................ 252
Figure 18.14. P1MDOUT: Port1 Output Mode Register ......................................... 253
Figure 18.15. P2: Port2 Data Register ................................................................... 253
Rev. 1.3
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