C8051F120 Datasheet, PDF (353/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Document Change List
Revision 1.2 to Revision 1.3
• Added four part numbers: C8051F130, C8051F131, C8051F132, and C8051F133.
• Modified all sections to describe functionality of the four new parts.
• Revised and expanded Flash Chapter with clearer descriptions of Flash security features.
• Incorporated VREF sections into single chapter.
• Global DC Electrical Characteristics Tables: Maximum external input frequency (Note 2 in tables)
extended to 30 MHz from 25 MHz.
• Global DC Electrical Characteristics Tables: Updated supply current specifications with characteriza-
tion data.
• SAR12 Chapter: Figure 5.2 updated with more generic drawing. Text updated to reflect new drawing
and points to specification table for Slope and Offset parameters.
• SAR12 Chapter: Table 5.1, “ADC0 Electrical Characteristics”: Temperature sensor characteristics sep-
arated into “Slope”, “Slope Error”, “Offset”, and “Offset Error”.
• SAR10 Chapter: Figure 6.11: Single-ended example mid-scale output for LJST = 0 changed from
“0x0800” to “0x0200”.
• SAR10 Chapter: Figure 6.2 updated with more generic drawing. Text updated to reflect new drawing
and points to specification table for Slope and Offset parameters.
• SAR10 Chapter: Table 6.1, “ADC0 Electrical Characteristics”: Temperature sensor characteristics sep-
arated into “Slope”, “Slope Error”, “Offset”, and “Offset Error”.
• SAR8 Chapter: Table 7.1, “ADC2 Electrical Characteristics”: SAR Clock MAX specification corrected to
“6 MHz”.
• SAR8 Chapter: ADC2CF Register Description: SAR Clock maximum corrected to read “6 MHz”.
• SAR8 Chapter: ADC2 Electrical Characteristics Table: Updated Offset Tempco and Signal-to-Noise
Plus Distortion specifications.
• CIP51 Chapter: Section 11.8.1: Added note regarding IDLE mode operation.
• CIP51 Chapter: Table 11.2: MAC0RNDL and MAC0RNDH locations corrected. Correct locations are
MAC0RNDL = 0xCE, MAC0RNDH = 0xCF, both on SFRPAGE 3.
• MAC0 Chapter, Section 12.3: Description of the MAC0CA bit was corrected. The MAC0CA bit will
immediately clear the contents of the MAC accumulator and the MAC0STA register. MAC0CA is
cleared to ‘0’ when the operation is complete.
• MAC0 Chapter, Section 12.5: Added text indicating that after a shift operation is complete, MAC0SC is
cleared to ‘0’.
• MAC0 Chapter, MAC0STA Register Description: Corrected MAC0SO text: This bit is set when an over-
flow occurs into the sign bit of the accumulator (bit 31) instead of into the MAC0OVR register.
• Timers Chapter: All references to “DCEN” and “DECEN” corrected to “DCENn”.
• Timers Chapter, Equation 23.1: Equation was corrected to “Fsq = Ftclk / (2*(65536-RCAPn))”. This
equation is valid for a timer counting up or down.
• Timers Chapter, Figure 23.14 TMRnCF: Corrected Bit 1 description. For square-wave output, CP/RLn
= 0, C/Tn = 0, TnOE = 1.
• Timers Chapter, Figure 23.12: “SMBus (Timer 4 Only)” changed to “SMBus (Timer 3 Only)”.
• DACs Chapter, Table 8.1 “DAC Electrical Characteristics”: Changed “Gain Error” to “Full-Scale Error”.
• Reset Sources Chapter: RSTSRC Register Description: PORSF bit permissions changed to “R/W”
from “R”.
• Reset Sources Chapter: Section 13.1: Added text to clarify use of PORSF bit to enable VDD Monitor
as a reset source.
• Port I/O Chapter, Section 18.2: Added a note in text body that Port 4-7 registers are all on SFR Page F.
Rev. 1.3
353