C8051F120 Datasheet, PDF (331/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
24. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. PCA0 consists of a dedicated 16-bit counter/timer and
six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled (See Section “18.1. Ports 0 through
3 and the Priority Crossbar Decoder” on page 242). The counter/timer is driven by a programmable time-
base that can select between six inputs as its source: system clock, system clock divided by four, system
clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or an external
clock signal on the ECI line. Each capture/compare module may be configured to operate independently in
one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit
PWM, or 16-Bit PWM (each is described in Section 24.2). The PCA is configured and controlled through
the system controller's Special Function Registers. The basic PCA block diagram is shown in Figure 24.1.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
PCA
CLOCK
MUX
16-Bit Counter/Timer
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
Capture/Compare
Module 5
Crossbar
Port I/O
Figure 24.1. PCA Block Diagram
Rev. 1.3
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