C8051F120 Datasheet, PDF (288/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
NSS
T
SE
SCK*
T
CKH
T
CKL
T
SIS
T
SIH
MOSI
MISO
T
SEZ
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 20.15. SPI Slave Timing (CKPHA = 0)
T
SD
T
SDZ
NSS
T
T
T
SE
CKL
SD
SCK*
T
CKH
T
SIS
T
SIH
MOSI
T
SEZ
MISO
T
SOH
T
SLH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 20.16. SPI Slave Timing (CKPHA = 1)
T
SDZ
288
Rev. 1.3