C8051F120 Datasheet, PDF (354/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
• Port I/O Chapter, Crossbar examples: References to “ADC1” and “AIN1” corrected to read “ADC2” and
“AIN2”.
• Port I/O Chapter, Figure 18.12, Port 1 Data Register: References to “AIN1” corrected to read “AIN2”.
• UART0 Chapter, Section 21.3: Error detection descriptions corrected. On this device, the bits FE0,
TXCOL0, and RXOV0 are all in SSTA0 (not SCON0), and they are not dual-purpose bits.
• UART0 Chapter: Updated and clarified baud rate equations.
• Oscillators Chapter, Table 14.1, Oscillator Electrical Characteristics: MAX External Clock frequency
extended to 30 MHz.
• Oscillators Chapter, Table 14.1, Oscillator Electrical Characteristics: MIN T_XCH and T_XCL changed to
15 ns.
• Oscillators Chapter, Section 14.7.3: Added note that when changing the FLRT bits to a lower setting,
cache reads, cache writes, and the prefetch engine should be disabled.
• Flash Chapter, FLSCL register description: Added note that when changing the FLRT bits to a lower
setting, cache reads, cache writes, and the prefetch engine should be disabled.
• Voltage Reference Chapter; Table 9.1, Voltage Reference Electrical Characteristics: Added power sup-
ply rejection for internal VREF and typical power supply current for bias generator and reference
buffer.
354
Rev. 1.3