C8051F120 Datasheet, PDF (302/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x99
SFR Page: 0
Bits7-0:
SBUF0.[7:0]: UART0 Buffer Bits 7-0 (MSB-LSB)
This is actually two registers; a transmit and a receive buffer register. When data is moved
to SBUF0, it goes to the transmit buffer and is held for serial transmission. Moving a byte to
SBUF0 is what initiates the transmission. When data is moved from SBUF0, it comes from
the receive buffer.
Figure 21.10. SBUF0: UART0 Data Buffer Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xA9
SFR Page: 0
Bits7-0:
SADDR0.[7:0]: UART0 Slave Address
The contents of this register are used to define the UART0 slave address. Register SADEN0
is a bit mask to determine which bits of SADDR0 are checked against a received address:
corresponding bits set to logic 1 in SADEN0 are checked; corresponding bits set to logic 0
are “don’t cares”.
Figure 21.11. SADDR0: UART0 Slave Address Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xB9
SFR Page: 0
Bits7-0:
SADEN0.[7:0]: UART0 Slave Address Enable
Bits in this register enable corresponding bits in register SADDR0 to determine the UART0
slave address.
0: Corresponding bit in SADDR0 is a “don’t care”.
1: Corresponding bit in SADDR0 is checked against a received address.
Figure 21.12. SADEN0: UART0 Slave Address Enable Register
302
Rev. 1.3