C8051F120 Datasheet, PDF (157/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 11.4. Interrupt Summary
Interrupt Source
Interrupt
Vector
Priority
Order
Pending Flags
Enable
Flag
Priority
Control
Reset
0x0000
External Interrupt 0 (/INT0)
Timer 0 Overflow
External Interrupt 1 (/INT1)
Timer 1 Overflow
0x0003
0x000B
0x0013
0x001B
UART0
0x0023
Timer 2
0x002B
Serial Peripheral Interface 0x0033
SMBus Interface
0x003B
ADC0 Window Comparator 0x0043
PCA 0
0x004B
Comparator 0 Falling Edge 0x0053
Comparator 0 Rising Edge 0x005B
Comparator 1 Falling Edge 0x0063
Comparator 1 Rising Edge 0x006B
Timer 3
0x0073
ADC0 End of Conversion 0x007B
Timer 4
0x0083
ADC2 Window Comparator 0x008B
ADC2 End of Conversion
RESERVED
UART1
0x0093
0x009B
0x00A3
Top None
N/A
N/A
Always
Enabled
Always
Highest
0 IE0 (TCON.1)
Y Y EX0 (IE.0) PX0 (IP.0)
1 TF0 (TCON.5)
Y Y ET0 (IE.1) PT0 (IP.1)
2 IE1 (TCON.3)
Y Y EX1 (IE.2) PX1 (IP.2)
3 TF1 (TCON.7)
Y Y ET1 (IE.3) PT1 (IP.3)
4
RI0 (SCON0.0)
TI0 (SCON0.1)
Y
ES0 (IE.4) PS0 (IP.4)
5
TF2 (TMR2CN.7)
EXF2 (TMR2CN.6)
Y
ET2 (IE.5) PT2 (IP.5)
SPIF (SPI0CN.7)
6
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
Y
ESPI0
PSPI0
(EIE1.0) (EIP1.0)
RXOVRN (SPI0CN.4)
7 SI (SMB0CN.3)
Y
ESMB0 PSMB0
(EIE1.1) (EIP1.1)
8
AD0WINT
(ADC0CN.1)
Y
EWADC0 PWADC0
(EIE1.2) (EIP1.2)
9
CF (PCA0CN.7)
CCFn (PCA0CN.n)
Y
EPCA0 PPCA0
(EIE1.3) (EIP1.3)
10 CP0FIF (CPT0CN.4) Y
ECP0F PCP0F
(EIE1.4) (EIP1.4)
11 CP0RIF (CPT0CN.5) Y
ECP0R PCP0R
(EIE1.5) (EIP1.5)
12 CP1FIF (CPT1CN.4) Y
ECP1F PCP1F
(EIE1.6) (EIP1.6)
13 CP1RIF (CPT1CN.5) Y
ECP1R PCP1F
(EIE1.7) (EIP1.7)
14
TF3 (TMR3CN.7)
EXF3 (TMR3CN.6)
Y
ET3
PT3
(EIE2.0) (EIP2.0)
15 AD0INT (ADC0CN.5) Y
EADC0 PADC0
(EIE2.1) (EIP2.1)
16
TF4 (TMR4CN.7)
EXF4 (TMR4CN.7)
Y
ET4
PT4
(EIE2.2) (EIP2.2)
17
AD2WINT
(ADC2CN.0)
Y
EWADC2 PWADC2
(EIE2.3) (EIP2.3)
18 AD2INT (ADC2CN.5) Y
EADC2 PADC2
(EIE2.4) (EIP2.4)
19 N/A
N/A N/A N/A
N/A
20
RI1 (SCON1.0)
TI1 (SCON1.1)
Y
ES1
PS1
(EIE2.6) (EIP2.6)
Rev. 1.3
157