C8051F120 Datasheet, PDF (341/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
CIDL
-
-
-
CPS2
CPS1
CPS0
ECF 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xD9
SFR Page: 0
Bit7:
Bits6-4:
Bits3-1:
CIDL: PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.
UNUSED. Read = 000b, Write = don't care.
CPS2-CPS0: PCA0 Counter/Timer Pulse Select.
These bits select the timebase source for the PCA0 counter
Bit0:
CPS2
0
0
0
0
1
1
1
1
CPS1
0
0
1
1
0
0
1
1
CPS0
0
1
0
1
0
1
0
1
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock
divided by 4)
System clock
External clock divided by 8 (synchronized with system
clock)
Reserved
Reserved
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
Figure 24.11. PCA0MD: PCA0 Mode Register
Rev. 1.3
341