C8051F120 Datasheet, PDF (196/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
R/W
PLLN7
Bit7
R/W
PLLN6
Bit6
R/W
PLLN5
Bit5
R/W
PLLN4
Bit4
R/W
PLLN3
Bit3
R/W
PLLN2
Bit2
R/W
PLLN1
Bit1
R/W
Reset Value
PLLN0 00000001
Bit0
SFR Address: 0x8E
SFR Page: F
Bits 7-0: PLLN7-0: PLL Multiplier.
These bits select the multiplication factor of the divided PLL reference clock. When set to
any non-zero value, the multiplication factor will be equal to the value in PLLN7-0. When set
to ‘00000000b’, the multiplication factor will be equal to 256.
Figure 14.9. PLL0MUL: PLL Clock Scaler Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
PLLICO1 PLLICO0 PLLLP3 PLLLP2 PLLLP1 PLLLP0 00110001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x8F
SFR Page: F
Bits 7-6: UNUSED: Read = 00b; Write = don’t care.
Bits 5-4: PLLICO1-0: PLL Current-Controlled Oscillator Control Bits.
Selection is based on the desired output frequency, according to the following table:
PLL Output Clock
65–100 MHz
45–80 MHz
30–60 MHz
25–50 MHz
PLLICO1-0
00
01
10
11
Bits 3-0: PLLLP3-0: PLL Loop Filter Control Bits.
Selection is based on the divided PLL reference clock, according to the following table:
Divided PLL Reference Clock
19–30 MHz
12.2–19.5 MHz
7.8–12.5 MHz
5–8 MHz
PLLLP3-0
0001
0011
0111
1111
Figure 14.10. PLL0FLT: PLL Filter Register
198
Rev. 1.3