C8051F120 Datasheet, PDF (41/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 3.2. Global DC Electrical Characteristics (C8051F124/5/6/7)
-40°C to +85°C, 50 MHz System Clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max Units
Analog Supply Voltage
(Note 1)
2.7
3.0
3.6
V
Analog Supply Current
Internal REF, ADC, DAC, Com-
1.7
mA
parators all active
Analog Supply Current with Internal REF, ADC, DAC, Com-
0.2
µA
analog sub-systems inactive parators all disabled, oscillator
disabled
Analog-to-Digital Supply
Delta (|VDD - AV+|)
0.5
V
Digital Supply Voltage
2.7
3.0
3.6
V
Digital Supply Current with VDD=3.0 V, Clock=50 MHz
35
mA
CPU active
VDD=3.0 V, Clock=1 MHz
1
mA
VDD=3.0 V, Clock=32 kHz
33
µA
Digital Supply Current with VDD=3.0 V, Clock=50 MHz
CPU inactive (not accessing VDD=3.0 V, Clock=1 MHz
FLASH)
VDD=3.0 V, Clock=32 kHz
27
mA
0.4
mA
15
µA
Digital Supply Current (shut- Oscillator not running
down)
0.4
µA
Digital Supply RAM Data
Retention Voltage
1.5
V
SYSCLK (System Clock)
(Notes 2 and 3)
0
50
MHz
Specified Operating Temper-
ature Range
-40
+85
°C
Note 1: Analog Supply AV+ must be greater than 1 V for VDD monitor to operate.
Note 2: SYSCLK is the internal device clock. For operational speeds in excess of 30 MHz, SYSCLK must
be derived from the Phase-Locked Loop (PLL).
Note 3: SYSCLK must be at least 32 kHz to enable debugging.
Rev. 1.3
41