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C8051F120 Datasheet, PDF (298/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family | |||
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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
address as valid. If a master were to then send an address of â11111111â, all three slave devices would rec-
ognize the address as a valid broadcast address.
Master
Device
RX
TX
Slave
Device
RX
TX
Slave
Device
RX
TX
Slave
Device
+5V
RX
TX
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram
21.3. Frame and Transmission Error Detection
All Modes:
The Transmit Collision bit (TXCOL0 bit in register SSTA0) reads â1â if user software writes data to the
SBUF0 register while a transmit is in progress.
Modes 1, 2, and 3:
The Receive Overrun bit (RXOV0 in register SSTA0) reads â1â if a new data byte is latched into the receive
buffer before software has read the previous byte. The Frame Error bit (FE0 in register SSTA0) reads â1â if
an invalid (low) STOP bit is detected.
298
Rev. 1.3
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