C8051F120 Datasheet, PDF (127/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Page: 2
SFR Address: 0x89
R/W
R/W
R/W
R/W
R/W
-
-
CP1RIE CP1FIE
-
Bit7
Bit6
Bit5
Bit4
Bit3
R/W
R/W
R/W
Reset Value
-
CP1MD1 CP1MD0 00000010
Bit2
Bit1
Bit0
Bits7-6:
Bit 5:
Bit 4:
Bits3-2:
Bits1-0:
UNUSED. Read = 00b, Write = don’t care.
CP1RIE: Comparator 1 Rising-Edge Interrupt Enable Bit.
0: Comparator 1 rising-edge interrupt disabled.
1: Comparator 1 rising-edge interrupt enabled.
CP1FIE: Comparator 0 Falling-Edge Interrupt Enable Bit.
0: Comparator 1 falling-edge interrupt disabled.
1: Comparator 1 falling-edge interrupt enabled.
UNUSED. Read = 00b, Write = don’t care.
CP1MD1-CP1MD0: Comparator1 Mode Select
These bits select the response time for Comparator1.
Mode
0
1
2
3
CP0MD1
0
0
1
1
CP0MD0
0
1
0
1
Notes
Fastest Response Time
-
-
Lowest Power Consumption
Figure 10.6. CPT1MD: Comparator1 Mode Selection Register
Rev. 1.3
127