C8051F120 Datasheet, PDF (100/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Page:
SFR Address:
R/W
AD2EN
Bit7
2
0xE8
R/W
AD2TM
Bit6
(bit addressable)
R/W
R/W
AD2INT AD2BUSY
Bit5
Bit4
R/W
AD2CM2
Bit3
R/W
AD2CM1
Bit2
R/W
AD2CM0
Bit1
R/W
Reset Value
AD2WINT 00000000
Bit0
Bit7:
Bit6:
Bit5:
Bit4:
Bits3-1:
Bit0:
AD2EN: ADC2 Enable Bit.
0: ADC2 Disabled. ADC2 is in low-power shutdown.
1: ADC2 Enabled. ADC2 is active and ready for data conversions.
AD2TM: ADC2 Track Mode Bit.
0: Normal Track Mode: When ADC2 is enabled, tracking is continuous unless a conversion
is in process.
1: Low-power Track Mode: Tracking Defined by AD2CM2-0 bits (see below).
AD2INT: ADC2 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC2 has not completed a data conversion since the last time this flag was cleared.
1: ADC2 has completed a data conversion.
AD2BUSY: ADC2 Busy Bit.
Read:
0: ADC2 Conversion is complete or a conversion is not currently in progress. AD2INT is set
to logic 1 on the falling edge of AD2BUSY.
1: ADC2 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC2 Conversion if AD2CM2-0 = 000b
AD2CM2-0: ADC2 Start of Conversion Mode Select.
AD2TM = 0:
000: ADC2 conversion initiated on every write of ‘1’ to AD2BUSY.
001: ADC2 conversion initiated on overflow of Timer 3.
010: ADC2 conversion initiated on rising edge of external CNVSTR2.
011: ADC2 conversion initiated on overflow of Timer 2.
1xx: ADC2 conversion initiated on write of ‘1’ to AD0BUSY (synchronized with ADC0 soft-
ware-commanded conversions).
AD2TM = 1:
000: Tracking initiated on write of ‘1’ to AD2BUSY for 3 SAR2 clocks, followed by conver-
sion.
001: Tracking initiated on overflow of Timer 3 for 3 SAR2 clocks, followed by conversion.
010: ADC2 tracks only when CNVSTR2 input is logic low; conversion starts on rising
CNVSTR2 edge.
011: Tracking initiated on overflow of Timer 2 for 3 SAR2 clocks, followed by conversion.
1xx: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR2 clocks, followed by con-
version.
AD2WINT: ADC2 Window Compare Interrupt Flag.
This bit must be cleared by software.
0: ADC2 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC2 Window Comparison Data match has occurred.
Figure 7.7. ADC2CN: ADC2 Control Register
100
Rev. 1.3