C8051F120 Datasheet, PDF (170/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
sign-extended with the current value of bit 39. Note that the status flags in the MAC0STA register are not
affected by shift operations.
12.6. Rounding and Saturation
A Rounding Engine is included, which can be used to provide a rounded result when operating on frac-
tional numbers. MAC0 uses an unbiased rounding algorithm to round the data stored in bits 31-16 of the
accumulator, as shown in Table 12.1. Rounding occurs during the third stage of the MAC0 pipeline, after
any shift operation, or on a write to the LSB of the accumulator. The rounded results are stored in the
rounding registers: MAC0RNDH (Figure 12.19) and MAC0RNDL (Figure 12.20). The accumulator regis-
ters are not affected by the rounding engine. Although rounding is primarily used for fractional data, the
data in the rounding registers is updated in the same way when operating in integer mode.
Table 12.1. MAC0 Rounding (MAC0SAT = 0)
Accumulator Bits 15-0
Accumulator Bits 31-16
Rounding Rounded Results
(MAC0ACC1:MAC0ACC0) (MAC0ACC3:MAC0ACC2) Direction (MAC0RNDH:MAC0RNDL)
Greater Than 0x8000
Anything
Up
(MAC0ACC3:MAC0ACC2) + 1
Less Than 0x8000
Anything
Down
(MAC0ACC3:MAC0ACC2)
Equal To 0x8000
Odd (LSB = 1)
Up
(MAC0ACC3:MAC0ACC2) + 1
Equal To 0x8000
Even (LSB = 0)
Down
(MAC0ACC3:MAC0ACC2)
The rounding engine can also be used to saturate the results stored in the rounding registers. If the
MAC0SAT bit is set to ‘1’ and the rounding register overflows, the rounding registers will saturate. When a
positive overflow occurs, the rounding registers will show a value of 0x7FFF when saturated. For a nega-
tive overflow, the rounding registers will show a value of 0x8000 when saturated. If the MAC0SAT bit is
cleared to ‘0’, the rounding registers will not saturate.
12.7. Usage Examples
This section details some software examples for using MAC0. Figure 12.5 shows a series of two MAC
operations using fractional numbers. Figure 12.6 shows a single operation in Multiply Only mode with inte-
ger numbers. The last example, shown in Figure 12.7, demonstrates how the left-shift and right-shift oper-
ations can be used to modify the accumulator. All of the examples assume that all of the flags in the
MAC0STA register are initially set to ‘0’.
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