C8051F120 Datasheet, PDF (5/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
13.4.Missing Clock Detector Reset ........................................................................ 183
13.5.Comparator0 Reset ........................................................................................ 183
13.6.External CNVSTR0 Pin Reset ........................................................................ 183
13.7.Watchdog Timer Reset................................................................................... 183
13.7.1.Enable/Reset WDT ................................................................................ 184
13.7.2.Disable WDT .......................................................................................... 184
13.7.3.Disable WDT Lockout ............................................................................ 184
13.7.4.Setting WDT Interval .............................................................................. 184
14. Oscillators ............................................................................................................. 189
14.1.Internal Calibrated Oscillator .......................................................................... 189
14.2.External Oscillator Drive Circuit...................................................................... 191
14.3.System Clock Selection.................................................................................. 191
14.4.External Crystal Example ............................................................................... 194
14.5.External RC Example ..................................................................................... 194
14.6.External Capacitor Example ........................................................................... 194
14.7.Phase-Locked Loop (PLL).............................................................................. 195
14.7.1.PLL Input Clock and Pre-divider ............................................................ 195
14.7.2.PLL Multiplication and Output Clock ...................................................... 195
14.7.3.Powering on and Initializing the PLL ...................................................... 196
15. FLASH Memory..................................................................................................... 201
15.1.Programming The Flash Memory ................................................................... 201
15.1.1.Non-volatile Data Storage ...................................................................... 202
15.1.2.Erasing FLASH Pages From Software................................................... 203
15.1.3.Writing FLASH Memory From Software................................................. 204
15.2.Security Options ............................................................................................. 205
15.2.1.Summary of Flash Security Options....................................................... 209
16. Branch Target Cache ........................................................................................... 213
16.1.Cache and Prefetch Operation ....................................................................... 213
16.2.Cache and Prefetch Optimization................................................................... 214
17. External Data Memory Interface and On-Chip XRAM........................................ 221
17.1.Accessing XRAM............................................................................................ 221
17.1.1.16-Bit MOVX Example ........................................................................... 221
17.1.2.8-Bit MOVX Example ............................................................................. 221
17.2.Configuring the External Memory Interface .................................................... 221
17.3.Port Selection and Configuration.................................................................... 222
17.4.Multiplexed and Non-multiplexed Selection.................................................... 225
17.4.1.Multiplexed Configuration....................................................................... 225
17.4.2.Non-multiplexed Configuration............................................................... 226
17.5.Memory Mode Selection................................................................................. 227
17.5.1.Internal XRAM Only ............................................................................... 227
17.5.2.Split Mode without Bank Select.............................................................. 227
17.5.3.Split Mode with Bank Select................................................................... 228
17.5.4.External Only.......................................................................................... 228
17.6.EMIF Timing ................................................................................................... 229
17.6.1.Non-multiplexed Mode ........................................................................... 230
Rev. 1.3
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