C8051F120 Datasheet, PDF (176/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x96
SFR Page: 3
Bits 7-0: Byte 3 (bits 31-24) of MAC0 Accumulator.
Note: The contents of this register should not be changed by software during the first two MAC0 pipe-
line stages.
Figure 12.14. MAC0ACC3: MAC0 Accumulator Byte 3 Register
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x95
SFR Page: 3
Bits 7-0: Byte 2 (bits 23-16) of MAC0 Accumulator.
Note: The contents of this register should not be changed by software during the first two MAC0 pipe-
line stages.
Figure 12.15. MAC0ACC2: MAC0 Accumulator Byte 2 Register
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x94
SFR Page: 3
Bits 7-0: Byte 1 (bits 15-8) of MAC0 Accumulator.
Note: The contents of this register should not be changed by software during the first two MAC0 pipe-
line stages.
Figure 12.16. MAC0ACC1: MAC0 Accumulator Byte 1 Register
178
Rev. 1.3