C8051F120 Datasheet, PDF (177/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x93
SFR Page: 3
Bits 7-0: Byte 0 (bits 7-0) of MAC0 Accumulator.
Note: The contents of this register should not be changed by software during the first two MAC0 pipe-
line stages.
Figure 12.17. MAC0ACC0: MAC0 Accumulator Byte 0 Register
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x97
SFR Page: 3
Bits 7-0: MAC0 Accumulator Overflow Bits (bits 39-32).
Note: The contents of this register should not be changed by software during the first two MAC0 pipe-
line stages.
Figure 12.18. MAC0OVR: MAC0 Accumulator Overflow Register
R
R
R
R
R
R
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bits 7-0: High Byte (bits 15-8) of MAC0 Rounding Register.
R
R
Reset Value
00000000
Bit1
Bit0
SFR Address: 0xCF
SFR Page: 3
Figure 12.19. MAC0RNDH: MAC0 Rounding Register High Byte
Rev. 1.3
179