C8051F120 Datasheet, PDF (258/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
R/W
P6.7
Bit7
R/W
P6.6
Bit6
R/W
P6.5
Bit5
R/W
P6.4
Bit4
R/W
P6.3
Bit3
R/W
P6.2
Bit2
R/W
P6.1
Bit1
R/W
Reset Value
P6.0 11111111
Bit0
Bit
Addressable
SFR Address: 0xE8
SFR Page: F
Bits7-0:
P6.[7:0]: Port6 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P6MDOUT bit = 0). See Figure 18.24.
Read - Returns states of I/O pins.
0: P6.n pin is logic low.
1: P6.n pin is logic high.
Note:
P6.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multi-
plexed mode, or as Address[7:0] in Non-multiplexed mode). See Section “17. External Data
Memory Interface and On-Chip XRAM” on page 221 for more information about the External
Memory Interface.
Figure 18.23. P6: Port6 Data Register
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bits7-0: P6MDOUT.[7:0]: Port6 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
R/W
R/W
Reset Value
00000000
Bit1
Bit0
SFR Address: 0x9E
SFR Page: F
Figure 18.24. P6MDOUT: Port6 Output Mode Register
260
Rev. 1.3