C8051F120 Datasheet, PDF (87/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Page: 0
SFR Address: 0xC6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits7-0: Low byte of ADC0 Less-Than Data Word.
Figure 6.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register
Input Voltage
(AD0.0 - AGND)
REF x (1023/1024)
ADC Data
Word
0x03FF
ADWINT
not affected
REF x (512/1024)
REF x (256/1024)
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
ADC0LTH:ADC0LTL
ADWINT=1
ADC0GTH:ADC0GTL
ADWINT
not affected
0
0x0000
Given:
AMX0SL = 0x00, AMX0CF = 0x00
AD0LJST = ‘0’,
ADC0LTH:ADC0LTL = 0x0200,
ADC0GTH:ADC0GTL = 0x0100.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0x0200 and > 0x0100.
Input Voltage
(AD0.0 - AGND)
REF x (1023/1024)
ADC Data
Word
0x03FF
ADWINT=1
REF x (512/1024)
REF x (256/1024)
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
ADC0GTH:ADC0GTL
ADWINT
not affected
ADC0LTH:ADC0LTL
ADWINT=1
0
0x0000
Given:
AMX0SL = 0x00, AMX0CF = 0x00,
AD0LJST = ‘0’,
ADC0LTH:ADC0LTL = 0x0100,
ADC0GTH:ADC0GTL = 0x0200.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
> 0x0200 or < 0x0100.
Figure 6.16. 10-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data
Rev. 1.3
87