C8051F120 Datasheet, PDF (251/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
R/W
P1.7
Bit7
R/W
P1.6
Bit6
R/W
P1.5
Bit5
R/W
P1.4
Bit4
R/W
P1.3
Bit3
R/W
P1.2
Bit2
R/W
P1.1
Bit1
R/W
Reset Value
P1.0 11111111
Bit0
Bit
Addressable
SFR Address: 0x90
SFR Page: All Pages
Bits7-0:
P1.[7:0]: Port1 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P1MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P1.n pin is logic low.
1: P1.n pin is logic high.
Notes:
1.
2.
On C8051F12x devices, P1.[7:0] can be configured as inputs to ADC2 as AIN2.[7:0], in
which case they are ‘skipped’ by the Crossbar assignment process and their digital input
paths are disabled, depending on P1MDIN (See Figure 18.13). Note that in analog mode,
the output mode of the pin is determined by the Port 1 latch and P1MDOUT (Figure 18.14).
See Section “7. ADC2 (8-Bit ADC, C8051F12x Only)” on page 93 for more information about
ADC2.
P1.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-mul-
tiplexed mode). See Section “17. External Data Memory Interface and On-Chip XRAM” on
page 221 for more information about the External Memory Interface.
Figure 18.12. P1: Port1 Data Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR
Address:
SFR Page:
0xAD
F
Bits7-0:
P1MDIN.[7:0]: Port 1 Input Mode Bits.
0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from
the Port bit will always return ‘0’). The weak pull-up on the pin is disabled.
1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic
level at the Pin. When configured as a digital input, the state of the weak pull-up for the port
pin is determined by the WEAKPUD bit (XBR2.7, see Figure 18.9).
Figure 18.13. P1MDIN: Port1 Input Mode Register
Rev. 1.3
253