C8051F120 Datasheet, PDF (289/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 20.1. SPI Slave Timing Parameters
Parameter Description
Min
MASTER MODE TIMING^† (See Figure 20.12 and Figure 20.13)
T_MCKH
SCK High Time
1*T_SYSCLK
T_MCKL
SCK Low Time
1*T_SYSCLK
T_MIS
MISO Valid to SCK Shift Edge
1*T_SYSCLK +
20
T_MIH
SCK Shift Edge to MISO Change
0
SLAVE MODE TIMING^† (See Figure 20.14 and Figure 20.15)
T_SE
NSS Falling to First SCK Edge
2*T_SYSCLK
T_SD
Last SCK Edge to NSS Rising
2*T_SYSCLK
T_SEZ
NSS Falling to MISO Valid
T_SDZ
NSS Rising to MISO High-Z
T_CKH
SCK High Time
5*T_SYSCLK
T_CKL
SCK Low Time
5*T_SYSCLK
T_SIS
MOSI Valid to SCK Sample Edge
2*T_SYSCLK
T_SIH
SCK Sample Edge to MOSI Change
2*T_SYSCLK
T_SOH
SCK Shift Edge to MISO Change
T_SLH
Last SCK Edge to MISO Change (CKPHA = 1
ONLY)
6*T_SYSCLK
†_{TSYSCLK is equal to one period of the device system clock (SYSCLK).}
Max
Units
ns
ns
ns
ns
ns
ns
4*T_SYSCLK ns
4*T_SYSCLK ns
ns
ns
ns
ns
4*T_SYSCLK ns
8*T_SYSCLK ns
Rev. 1.3
289