C8051F120 Datasheet, PDF (15/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Figure 21.3. UART0 Mode 0 Interconnect.............................................................. 292
Figure 21.4. UART0 Mode 1 Timing Diagram ........................................................ 293
Figure 21.5. UART0 Modes 2 and 3 Timing Diagram ............................................ 295
Figure 21.6. UART0 Modes 1, 2, and 3 Interconnect Diagram .............................. 296
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................... 298
Figure 21.8. SCON0: UART0 Control Register ...................................................... 300
Figure 21.9. SSTA0: UART0 Status and Clock Selection Register........................ 301
Figure 21.10. SBUF0: UART0 Data Buffer Register .............................................. 302
Figure 21.11. SADDR0: UART0 Slave Address Register ...................................... 302
Figure 21.12. SADEN0: UART0 Slave Address Enable Register .......................... 302
22. UART1.................................................................................................................... 303
Figure 22.1. UART1 Block Diagram ....................................................................... 303
Figure 22.2. UART1 Baud Rate Logic .................................................................... 304
Figure 22.3. UART Interconnect Diagram .............................................................. 305
Figure 22.4. 8-Bit UART Timing Diagram............................................................... 305
Figure 22.5. 9-Bit UART Timing Diagram............................................................... 306
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram .......................... 307
Figure 22.7. SCON1: Serial Port 1 Control Register .............................................. 308
Figure 22.8. SBUF1: Serial (UART1) Port Data Buffer Register ............................ 309
23. Timers.................................................................................................................... 313
Figure 23.1. T0 Mode 0 Block Diagram.................................................................. 314
Figure 23.2. T0 Mode 2 Block Diagram.................................................................. 315
Figure 23.3. T0 Mode 3 Block Diagram.................................................................. 316
Figure 23.4. TCON: Timer Control Register ........................................................... 317
Figure 23.5. TMOD: Timer Mode Register ............................................................. 318
Figure 23.6. CKCON: Clock Control Register ........................................................ 319
Figure 23.7. TL0: Timer 0 Low Byte ....................................................................... 320
Figure 23.8. TL1: Timer 1 Low Byte ....................................................................... 320
Figure 23.9. TH0: Timer 0 High Byte...................................................................... 320
Figure 23.10. TH1: Timer 1 High Byte.................................................................... 321
Figure 23.11. T2, 3, and 4 Capture Mode Block Diagram ...................................... 323
Figure 23.12. T2, 3, and 4 Auto-reload Mode Block Diagram ................................ 324
Figure 23.13. TMRnCN: Timer 2, 3, and 4 Control Registers ................................ 326
Figure 23.14. TMRnCF: Timer 2, 3, and 4 Configuration Registers ....................... 327
Figure 23.15. RCAPnL: Timer 2, 3, and 4 Capture Register Low Byte .................. 328
Figure 23.16. RCAPnH: Timer 2, 3, and 4 Capture Register High Byte................. 328
Figure 23.17. TMRnL: Timer 2, 3, and 4 Low Byte................................................. 328
Figure 23.18. TMRnH Timer 2, 3, and 4 High Byte ................................................ 329
24. Programmable Counter Array ............................................................................. 331
Figure 24.1. PCA Block Diagram............................................................................ 331
Figure 24.2. PCA Counter/Timer Block Diagram.................................................... 332
Figure 24.3. PCA Interrupt Block Diagram ............................................................. 333
Figure 24.4. PCA Capture Mode Diagram.............................................................. 334
Figure 24.5. PCA Software Timer Mode Diagram .................................................. 335
Figure 24.6. PCA High Speed Output Mode Diagram............................................ 336
Rev. 1.3
15