C8051F120 Datasheet, PDF (136/356 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-
volatile data storage. Refer to Section “15. FLASH Memory” on page 201 for further details.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
COBANK
-
-
IFBANK
00010001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR
Address:
SFR Page:
0xB1
All Pages
Bits 7-6:
Bits 5-4:
Bits 3-2:
Bits 1-0:
Reserved.
COBANK: Constant Operations Bank Select.
These bits select which FLASH bank is targeted during constant operations (MOVC and FLASH
MOVX) involving addresses 0x8000 to 0xFFFF. These bits are ignored when accessing the
Scratchpad memory areas (see Section “15. FLASH Memory” on page 201).
00: Constant Operations Target Bank 0 (note that Bank 0 is also mapped between 0x0000 to
0x7FFF).
01: Constant Operations Target Bank 1.
10: Constant Operations Target Bank 2.
11: Constant Operations Target Bank 3.
Reserved.
IFBANK: Instruction Fetch Operations Bank Select.
These bits select which FLASH bank is used for instruction fetches involving addresses 0x8000
to 0xFFFF. These bits can only be changed from code in Bank 0 (see Figure 11.4).
00: Instructions Fetch From Bank 0 (note that Bank 0 is also mapped between 0x0000 to
0x7FFF).
01: Instructions Fetch From Bank 1.
10: Instructions Fetch From Bank 2.
11: Instructions Fetch From Bank 3.
Important Note: On the C8051F132/3, the COBANK and IFBANK bits should both remain set to the
default setting of ‘01’ to ensure proper device functionality.
Figure 11.3. PSBANK: Program Space Bank Select Register
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Rev. 1.3